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MC74LVX8053 Analog Multiplexer / Demultiplexer
High-Performance Silicon-Gate CMOS
The MC74LVX8053 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND). The LVX8053 is similar in pinout to the high-speed HC4053A, and the metal-gate MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pull-up resistors they are compatible with LSTTL outputs. This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches.
Features http://onsemi.com MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 LVX 8053 ALYW LVX8053 AWLYWW
* * * * * * * * * *
Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC - GND) = 2.5 to 6.0 V Digital (Control) Power Supply Range (VCC - GND) = 2.5 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts Low Noise In Compliance With the Requirements of JEDEC Standard No. 7A Chip Complexity: LVX8053 - 156 FETs or 39 Equivalent Gates Pb-Free Packages are Available*
16 SOEIAJ-16 M SUFFIX CASE 966 1 LVX8053 ALYW
A WL or L Y WW or W
= = = =
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
April, 2005 - Rev. 4
Publication Order Number: MC74LVX8053/D
MC74LVX8053
VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9
X0 13 X1 Y0 1 Y1 Z0 3 Z1 A 10 CHANNEL-SELECT B INPUTS 9 C 6 ENABLE
11 5 2
12
X SWITCH
14
X
1 Y1
2 Y0
3 Z1
4 Z
5 Z0
6 Enable
7 NC
8 GND
ANALOG INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON OUTPUTS/INPUTS
PIN CONNECTION AND MARKING DIAGRAM (Top View)
Z SWITCH
4
Z
FUNCTION TABLE - MC74LVX8053
PIN 16 = VCC PIN 8 = GND Control Inputs Enable L L L L L L L L H X = Don't Care C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1
NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch
LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off
ORDERING INFORMATION
Device MC74LVX8053DR2 MC74LVX8053DR2G MC74LVX8053DTR2 MC74LVX8053M MC74LVX8053MG MC74LVX8053MEL MC74LVX8053MELG Package SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX8053
IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
SymbolIIIIIIIIIIIIII Parameter VCC VIS Vin I Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) Value Unit V V V - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 500 450 Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, Storage Temperature Range mA PD SOIC Package TSSOP Package mW _C _C Tstg TL - 65 to + 150 260 Lead Temperature, 1 mm from Case for 10 Seconds Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
III I I I I I IIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I III I I I II I IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I
Symbol VCC VIS Vin Parameter Min 2.5 0.0 Max 6.0 Unit V V V V Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) VCC VCC 1.2 Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND VIO* TA Operating Temperature Range, All Package Types - 55 + 85 _C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V ns/V 0 0 100 20 *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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MC74LVX8053
DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND)
VCC V 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 5.5 5.5 Guaranteed Limit -55 to 25C 1.50 2.10 3.15 3.85 0.5 0.9 1.35 1.65 0.1 4 85C 1.50 2.10 3.15 3.85 0.5 0.9 1.35 1.65 1.0 40 125C 1.50 2.10 3.15 3.85 0.5 0.9 1.35 1.65 1.0 160 Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs
Condition Ron = Per Spec
VIL
Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs
Ron = Per Spec
V
Iin ICC
Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND, Channel Select, Enable and VIS = VCC or GND; VIO = 0 V
mA mA
DC ELECTRICAL CHARACTERISTICS Analog Section
III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII II I II II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II III I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I
Symbol Ron Parameter Test Conditions VCC V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 Guaranteed Limit v 85_C 45 32 28 35 28 25 20 12 12 -55 to 25C 40 30 25 30 25 20 125C 50 37 30 40 35 30 25 15 15 Unit W Maximum "ON" Resistance Vin = VIL or VIH VIS = VCC to GND |IS| v 10.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = VCC or GND (Endpoints) |IS| v 10.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC - GND) |IS| v 10.0 mA DRon Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package 15 8.0 8.0 W Ioff Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel Maximum On-Channel Leakage Current, Channel-to-Channel Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4) 0.1 0.5 1.0 mA 5.5 0.1 1.0 2.0 Ion Vin = VIL or VIH; Switch-to-Switch = VCC or GND; (Figure 5) 5.5 0.1 1.0 2.0 mA
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MC74LVX8053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) VCC V 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 Guaranteed Limit -55 to 25C 30 20 15 15 4.0 3.0 1.0 1.0 30 20 15 15 20 12 8.0 8.0 10 35 50 1.0 85C 35 25 18 18 6.0 5.0 2.0 2.0 35 25 18 18 25 14 10 10 10 35 50 1.0 125C 40 30 22 20 8.0 6.0 2.0 2.0 40 30 22 20 30 15 12 12 10 35 50 1.0 Unit ns
tPLH, tPHL
Maximum Propagation Delay, Analog Input to Analog Output (Figure 10)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Enable to Analog Output (Figure 11)
ns
tPZL, tPZH
Maximum Propagation Delay, Enable to Analog Output (Figure 11)
ns
Cin CI/O
Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I Feedthrough
pF pF
Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Figure 13)* 45 pF * Used to determine the no-load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
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MC74LVX8053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
VCC V Limit* 25C Unit MHz 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 120 120 120 -50 -50 -50 -37 -37 -37 25 105 135 35 145 190 -50 -50 -50 -60 -60 -60 % 3.0 4.5 5.5 0.10 0.08 0.05 dB mVPP dB
Symbol BW
Parameter Maximum On-Channel Bandwidth or Minimum F Mi i Frequency R Response (Figure 6)
Condition fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm t 0dB at VOS; I Increase fin Frequency Until dB F U til Meter Reads -3dB; RL = 50W, CL = 10pF fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600W, CL = 50pF
-
Off-Channel Feedthrough Isolation (Figure 7)
fin = 1.0MHz, RL = 50W, CL = 10pF - Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600W, CL = 50pF
RL = 10kW, CL = 10pF - Crosstalk Between Any Two Switches (Figure 12) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600W, CL = 50pF
fin = 1.0MHz, RL = 50W, CL = 10pF THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10kW, CL = 50pF THD = THDmeasured - THDsource VIS = 2.0VPP sine wave VIS = 4.0VPP sine wave VIS = 5.5VPP sine wave
*Limits not tested. Determined by design and verified by qualification.
45 40 Ron , ON RESISTANCE (OHMS) 35 30 25 20 15 10 5 00 1.0 2.0 VIN, INPUT VOLTAGE (VOLTS) 3.0 4.0 125C 85C 25C -55 C
Figure 1a. Typical On Resistance, VCC = 3.0 V
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MC74LVX8053
30 Ron , ON RESISTANCE (OHMS) 125C 85C 25C -55 C Ron , ON RESISTANCE (OHMS) 25 20 15 10 5 0 30 25 20 15 10 5 0 1.0 2.0 3.0 4.0 5.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 125C 85C 25C -55 C
VIN, INPUT VOLTAGE (VOLTS)
VIN, INPUT VOLTAGE (VOLTS)
Figure 1b. Typical On Resistance, VCC = 4.5 V
Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
VCC DEVICE UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set-Up
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MC74LVX8053
VCC VCC
GND OFF VCC A NC OFF
16
VCC
GND VCC
ANALOG I/O
16 OFF OFF
VCC
COMMON O/I
COMMON O/I
VIH
6 8
VIH
6 8
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up
VCC A ON GND VCC ANALOG I/O VIL 6 8 OFF
16
VCC fin COMMON O/I N/C
VCC 0.1mF ON 16
VOS dB METER CL* RL
6 8 *Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up
Figure 6. Maximum On Channel Bandwidth, Test Set-Up
VIS 0.1mF fin RL OFF
VCC 16
VOS dB METER CL* RL RL ON/OFF ANALOG I/O OFF/ON RL
VCC 16 COMMON O/I RL CL* TEST POINT
6 8 VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance VCC GND Vin 1 MHz tr = tf = 3 ns
6 8 11
VCC
CHANNEL SELECT *Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation, Test Set-Up
Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up
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MC74LVX8053
VCC VCC CHANNEL SELECT tPLH ANALOG OUT 50% 50% GND tPHL 6 8 CHANNEL SELECT *Includes all probe and jig capacitance ANALOG I/O OFF/ON CL* ON/OFF VCC 16 COMMON O/I TEST POINT
Figure 9a. Propagation Delays, Channel Select to Analog Out
Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out
VCC 16 ANALOG IN tPLH ANALOG OUT 50% VCC 50% GND tPHL 6 8 ANALOG I/O ON CL* COMMON O/I TEST POINT
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In to Analog Out
Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out
tf ENABLE tPZL ANALOG OUT 50%
tr 90% 50% 10% tPLZ VCC GND HIGH IMPEDANCE 10% tPZH tPHZ 90% 50% HIGH IMPEDANCE VOH VOL VCC 1 2 1 2
POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O ON/OFF CL* ENABLE
1kW TEST POINT
6 8
ANALOG OUT
Figure 11a. Propagation Delays, Enable to Analog Out
Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out
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MC74LVX8053
VCC VIS VCC fin 0.1mF OFF RL 6 8 *Includes all probe and jig capacitance RL CL* RL CL* 6 8 11 VCC RL ON 16 VOS ANALOG I/O OFF/ON ON/OFF 16 COMMON O/I NC A
CHANNEL SELECT
Figure 12. Crosstalk Between Any Two Switches, Test Set-Up
0 VCC 16 ON RL CL* VOS TO DISTORTION METER dB -10 -20 -30 -40 -50 -60 6 8 *Includes all probe and jig capacitance -70 -80 -90 - 100
Figure 13. Power Dissipation Capacitance, Test Set-Up
VIS 0.1mF fin
FUNDAMENTAL FREQUENCY
DEVICE SOURCE
1.0
2.0 FREQUENCY (kHz)
3.125
Figure 14a. Total Harmonic Distortion, Test Set-Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swing is determined by the supply voltages VCC. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In this example, the difference between VCC and GND is five volts. Therefore, using the configuration of Figure 15, a maximum analog signal of five volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts When voltage transients above VCC and/or below GND are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping.
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MC74LVX8053
+5V +5V 0V ANALOG SIGNAL 16 ON ANALOG SIGNAL +5V 0V VCC Dx Dx VEE 6 8 11 10 9 TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS VCC 16 ON/OFF Dx VEE VCC Dx
8
Figure 15. Application Example
Figure 16. External Germanium or Schottky Clipping Diodes
+5V +5V GND ANALOG SIGNAL 16 ON/OFF ANALOG SIGNAL +5V * R R +5V GND R LSTTL/NMOS CIRCUITRY 6 8 11 10 9 +5V GND ANALOG SIGNAL 16 ON/OFF
+5V ANALOG SIGNAL +5V GND +5V LSTTL/NMOS CIRCUITRY VHC1GT50 BUFFERS
6 8
11 10 9 * 2K R 10K
a. Using Pull-Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
A
11
LEVEL SHIFTER
13
X1
12 14 B 10 LEVEL SHIFTER 1
X0 X Y1
2 15 C 9 LEVEL SHIFTER 3
Y0 Y Z1
5 4 ENABLE 6 LEVEL SHIFTER
Z0 Z
Figure 18. Function Diagram, LVX8053
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MC74LVX8053
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
M
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC74LVX8053
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX8053
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MC74LVX8053/D

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